The present invention relates to a semiconductor integrated circuit such as a single chip microcomputer (hereinafter referred to as a microcomputer) having a built-in non-volatile memory such as a flash memory, an electronically erasable programmable read only memory (hereinafter referred to as EEPROM), an erasable programmable read only memory (hereinafter referred to as EPROM), or a ferroelectric random access memory (hereinafter referred to as FeRAM), and a central processing unit (hereinafter referred to as xe2x80x9cCPUxe2x80x9d) or gate array. In particular, the present invention relates to a semiconductor integrated circuit which has no work random access memory (hereinafter referred to as RAM) and which is capable of executing programs. The invention further relates to a method for writing into a non-volatile memory incorporated in such semiconductor integrated circuits.
Previously, semiconductor integrated circuits having a CPU and a non-volatile memory incorporated therein have been mounted on a board and then a ROM writer communicates with the CPU through a serial interface to operate the CPU for writing programs into the non-volatile memory or updating them. This is called xe2x80x9con-board (in-circuit) writingxe2x80x9d. As an example, FIG. 6 depicts an example of the circuit configuration for on-board writing.
In FIG. 6, a microcomputer 300 is formed of a CPU core 301, a control register 302, a synchronous serial communication interface 303, a multiplexer 304, a flash memory 305, and a mask ROM 307. The CPU core 301 is connected to the mask ROM 307 and the multiplexer 304 through an instruction address bus B31 and an instruction bus B32. Additionally, the CPU core 301 is connected to the control register 302, the synchronous serial communication interface 303, and the multiplexer 304 through a data address bus B33 and a data bus B34.
The multiplexer 304 is connected to the flash memory 305 through a bus B35. The flash memory 305 is a non-volatile memory for storing instruction codes that the CPU core 301 should execute or data that the CPU core 301 uses.
When a program is written into the flash memory 305, a ROM writer 400 is connected to the synchronous serial communication interface 303. The ROM writer 400 transfers operation commands, address information or data by synchronous serial communications. On the other hand, the mask ROM 307 incorporated in the microcomputer 300 is a read-only memory for storing programs executed by the CPU core 301 to perform on-board writing to the flash memory 305, and the mask ROM 307 is used for communications and sequencing. The operation commands that have been transferred from the ROM writer 400 to the microcomputer 300 are executed by the on-board writing program stored in the mask ROM 307 and erasing or data writing is peformed based on the address information. Management during writing or erasing is also performed by the programs stored in the mask ROM 307.
Synchronous serial communication uses a CLK signal line 404 for transmitting clocks from the ROM writer 400 to the microcomputer 300 a RXD signal line 401 for transmitting data from the ROM writer 400 to the microcomputer 300, a TXD signal line 402 for transmitting data from the microcomputer 300 to the ROM writer 400, and a SCLK signal line 403 for transmitting and receiving serial clocks between the ROM writer 400 and the microcomputer 300.
The control register 302 is connected to the CPU core 301 as described above, and is also connected to the multiplexer 304 through a flash memory writing address bus B36, a flash memory writing data bus B37, and a control signal bus B38. The control register 302 holds data written by the CPU core 301 and outputs the data to the flash memory writing address bus B36, the flash memory writing data bus B37, and the control signal bus B38.
The multiplexer 304 is connected to the CPU core 301 and the flash memory 305 as described above, and is also connected to a switch 308 through a flash memory writing mode designating line 306. The switch 308 is turned on (closed) to ground the flash memory writing mode designating line 306 when on-board writing is conducted, and it is turned off (opened) to pull up the flash memory writing mode designating line 306 through the pull up resistor when on-board writing is not conducted. The multiplexer 304 connects the buses B31 to B34 with the bus B35 when the flash memory writing mode designating line 306 is pulled up, while it connects the buses B36 to B38 with the bus B35 when the flash memory writing mode designating line 306 is grounded.
Next, the normal operation (an operation other than on-board writing) of the microcomputer 300 shown in FIG. 6 will be described. In addition, during normal operation, the switch 308 is turned off (opened) and the flash memory writing mode designating line 306 is pulled up.
First, the CPU core 301 outputs an instruction address on the instruction address bus B31. The multiplexer 304 transmits the instruction address outputted on the instruction address bus B31 to the bus B35. The flash memory 305 receives the instruction address from the bus B35 and outputs an instruction code corresponding to the address to the bus B35. The multiplexer 304 transmits the instruction code outputted on the bus B35 to the instruction bus B32. The CPU core 301 receives the instruction code from the instruction bus B32 and executes the instruction code. In this manner, the CPU core 301 executes a series of instruction codes (a program) stored in the flash memory 305.
Next, an on-board writing operation in the conventional example will be described. When on-board writing is performed, an on-board writing operator turns on (closed) the switch 308 and a power supply of the micro computer 300, and also turns on a power supply of the ROM writer 400 to start the operation.
When the on-board writing operation is started, the CPU core 301 outputs an address corresponding to the on-board writing program I the mask ROM 307 to the instruction address bus B31. Then, the CPU core 301 reads the instruction codes for on-board writing from the mask ROM 307 through the instruction bus B32. Subsequently, the CPU core 301 executes the read instruction codes for on-board writing. The CPU core 301 further receives data and the like required for on-board writing from the ROM writer 400 through synchronous serial communication lines 401 to 404 and the synchronous serial communication interface 303. In this manner, the CPU core 301 executes a series of instruction codes (a program) for on-board writing stored in the mask ROM 307, whereby writing the flash memory 305 is performed.
Accordingly, because the mask ROM is needed to store programs for executing communication and sequencing for on-board writing, the size of the circuit has been increased. In particular, the microcomputer has suffered from a problem in that as the chip area for incorporating the mask ROM increases, the number of terminals also increases.
Additionally, to change the pulse width of each control signal or the number of retries while performing on-board writing, programs stored in the mask ROM need to be altered. In regard to this, it can be considered that programs in the mask ROM are created beforehand to output each of the control signals with multiple kinds of pulse widths. However, there has been a problem in that as the program size increases, the mask ROM size also increases.
As a method for solving such problems, it can be considered that programs for on-board writing are stored in the RAM and executed. However, a 4-bit microcomputer is generally configured to have no work RAM. Besides, even when the RAM is included, the 4-bit microcomputer or the like has varying data widths and instruction widths and thus it has been difficult to store the programs for on-board writing in the RAM and to execute them.
Meanwhile, in a bootloader circuit described in Japanese Unexamined Patent Application Publication (Kokai) No. 11-149376, a ROM can be written by using an external communication interface but it cannot secure the pulse width of each control signal for writing the ROM, as described above.
In view of the points mentioned above, the object of the invention is to eliminate the need for a mask ROM when on-board writing is conducted to a non-volatile memory incorporated into a semiconductor integrated circuit, and to easily alter the pulse width of each control signal necessary to write into the non-volatile memory.
In order to solve the problems described above, a semiconductor integrated circuit in accordance with the present invention comprises a central processing unit (CPU), a non-volatile memory, and a communication interface for receiving a program to be executed by the CPU for writing onto the non-volatile memory by external communication and transmitting the received program to the CPU.
Here, the communication interface may receive the program to be executed by the CPU for writing into the non-volatile memory by external synchronous serial communications and transmits the received program to the CPU, and the communication interface may send serial clocks received by the synchronous serial communications to the CPU.
Additionally, a writing method in accordance with the present invention is a method for writing into a non-volatile memory incorporated in a semiconductor integrated circuit, the writing method comprising the steps of: (a) transmitting a program for writing into the non-volatile memory to a communication interface of the semiconductor integrated circuit by external communication; (b) sending the program received by the communication interface to a central processing unit (CPU) of the semiconductor integrated circuit; and (c) executing the received programs in the CPU to write into the non-volatile memory.
Here, step (a) may include the step of receiving the program for writing into the non-volatile memory be external synchronous serial communication, step (b) may include sending the program received by the communication interface to the CPU, and sending serial clocks received by the synchronous serial communications to the CPU, and step (c) may include executing the received program in the CPU with the serial clocks as operating clocks to write into the non-volatile memory.
According to the invention configured as described above, the program for writing into the non-volatile memory is transmitted by communication. Thus, the mask ROM or the like for storing the program for writing into the non-volatile memory can be eliminated, with the aim of simplifying the circuit or reducing the chip area. Thereby, a clock terminal for the mask ROM becomes unnecessary as well.
Additionally, it does not have fixed programs such as the programs stored in the mask ROM or the like and therefore problems with the programs are easily corrected.
Furthermore, the synchronous serial communication is used for transmitting the program for writing into the non-volatile memory to feed the serial clocks thereof to the CPU and to adjust the transmission timing of the program for writing into the non-volatile memory. Thereby, the pulse width of each of the control signals that are needed to write into the non-volatile memory is secured and the pulse width can be easily altered.